Executive Summary
AMD’s sixth generation EPYC processor, Verano, is the first in the line to carry LPDDR5X memory in replaceable SOCAMM2 modules. The chips are not shipping until 2027 and AMD has not published final specifications. The direction is still worth noting. For two years the AI rack was a GPU story, and the host CPU sat outside the power argument.
The memory move pulls it back in. Moving server memory to a low-power standard is a power decision before it is a bandwidth decision, and power is the constraint that decides how much compute fits inside a building. AMD is selling performance per system watt rather than peak core count, which is its own admission about where the bottleneck has moved.
AMD EPYC Verano is a Zen 6 part built for AI accelerator host nodes, the CPUs that feed work to the GPUs rather than the accelerators themselves. AMD pairs it with future AMD Instinct accelerators over 112 Gbps xGMI links. General availability is set for 2027.
The headline number is the core count, and AMD has not confirmed it. The demo part carried 192 cores, according to TechPowerUp. Earlier reporting pointed at a 72-core design. AMD’s published EPYC documentation does not settle the question, so treat 192 as shown rather than shipped.
LPDDR5X is a power move before it is a bandwidth one
The real change is memory. Verano is the first EPYC to use LPDDR5X, and AMD packages it in SOCAMM2 modules. SOCAMM2 is not a memory type. It is a form factor, a compact module with a compression connector that lets low-power memory be swapped like a DIMM instead of soldered to the board.
AMD’s own memory brief says LPDDR5X can improve server energy efficiency while still delivering high bandwidth, and that SOCAMM2 provides the serviceability data centers expect. Racks that run memory at a lower voltage free up power for the part that does the work. That is the argument in one line.
The memory bill moved from the accelerator to the host
This is where the rack math gets interesting. The KV cache that keeps inference fast has already outgrown GPU memory and spilled into host memory and storage, a shift we covered in our look at the KV cache and CXL. Once host memory is part of the serving path, its power draw stops being a footnote and becomes a constraint.
AMD is not first to SOCAMM2. Nvidia’s Vera CPU already uses the form factor, which tells you the two companies reached the same conclusion at the same time. When the host CPU and its memory are a meaningful slice of rack power, a low-power memory standard stops being an efficiency claim and becomes a design requirement.
The timing also fits the broader squeeze. Memory prices are climbing and rack power is the scarce input, a pair of pressures we have tracked in our work on the grid queue for AI campuses. A CPU that does more work per watt on the host side is one lever against both.
What to watch before 2027
Verano is not on a buying list yet. The core count is unsettled, SOCAMM2 is new to the EPYC socket, and few systems can take the modules today, a limit AMD states itself. The thing to track is not the spec sheet. It is whether the host node’s memory shows up as its own line on the rack power budget and the bill of materials, because that is what decides whether the CPU’s memory is a footnote or a cost center.
Three questions to take back to your own racks. What share of your power goes to host and memory rather than accelerators? If your serving stack leans on host memory for cache, have you priced its power against the GPU you gave up? And when you plan the next refresh, does the memory standard steer the decision, or only the CPU socket?
Get the next one before it is old news
Independent analysis of cloud-native infrastructure, Kubernetes and data center economics. No vendor spin.
[…] reading. AMD is making the same memory bet on the host side with LPDDR5X on SOCAMM2 modules. The reason capacity matters more than bandwidth is the KV cache spilling out of HBM. And […]